HT-Tech has fully independent intellectual property rights of wafer level fan-out packaging solution --eSiFO , whichcan provide customers with 8 "and 12"wafer level fan-out packaging services.

Advantages of fanout (eSiFO)

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Application Area

The eSiFO Package can be widely used for the PMIC，RF Transiver，BB and High-End network Chip etc.
Based on eSiFO technology，3D and SiP package applications can be realized by wafer level packaging technologies such as TSV and Bumping.

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Advanced Package -eSinC

Based on eSiFO technology platform, we develops 3D eSinC(embedded System in Chip) solution.

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Technical Characteristics

5dies are embedded in silicon with 2 layer RDL by wafer re-construction technology, LQFP was used as final package.